To obtain the truth-table shown, from the following logic circuit, the gate G should be array |l|l|l| A & B & Y 0 & 0 & 1 0 & 1 & 0 1 & 0 & 1 1 & 1 & 1 array

Step-by-step solution

The truth table for given configuration is as shown below. array |c|c|c|c|c| Case & A & B & C & A + C = Y I & 0 & 0 & C ₁ & 0+ C ₁=1 II & 0 & 1 & C ₂ & 0+ C ₂=0 III & 1 & 0 & C ₃ & 1+ C ₃=1 IV & 1 & 1 & C ₄ & 1+ C ₄=1 array Considering case (I), in order to have output Y ) as 1, C ₁ has to be 1 . For input values, A =0 and B =0 , if C ₁ is to be high, the gate G could be either NAND or NOR. Considering case (II), in order to have output (Y) as 0, C₂ has to be 0 . For input values, A =0 and B =1 . If C ₂ is to be 0