For the logic circuit shown, the output waveform at Y is

All the gates used in the diagram represent NAND gates.

Thus, the output $Y$ can be calculated as follows

$\begin{cases}Y & = & A \cdot B \\ & = & A + B \\ & = & A + B\end{cases}$

The above equation suggests that the output of the given combination yields the same result as an OR gate.

The truth table can be written as follows

$A$	$B$	$A$	$B$	$Y = A \cdot B$
$0$	$0$	$1$	$1$	$0$
$0$	$1$	$1$	$0$	$1$
$1$	$0$	$0$	$1$	$1$
$1$	$1$	$0$	$0$	$1$

Hence, this is the correct output.